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E L I T E C H A N N E L PA R T N E R simulation@rand.com | RandSIM.com | 888.483.0674 Keeping the prior conclusions in mind, we can better understand this benchmark graph: 1. The relative speedup is generally sublinear due to load balancing and communication impacts causing efficiency < 100% 2. The larger the mesh count, the further along the scaling goes before "falling off" 3. For small meshes, a higher core count can start to negatively affect speed Basically, all benchmarks will have similar trends to this, making it reasonably possible to predict speed increases. The primary variables affecting curvature are: • Model size • Increased interconnect speed • CPU architecture, cache, etc. • Memory bandwidth Adapted Methodologies Learning requires failing, and HPC supports failing faster and more often. The most capable and innovative design engineers are encouraged to tinker, test their ideas, and learn from failures. Learning about what doesn't work throughout the design process means the designer will know all the stay-out zones and the parameters that affect them. This knowledge is much more powerful than just knowing that a design works. An engineer with hundreds of cores at his fingertips is generally more willing to test multiple designs than someone with just four, because their testing time will be just minutes compared to days. The Analogy Design is a process that starts broadly and narrows in focus. Simulation can and should play a part in every step, because the more rapidly problems are solved, the more readily the answers will be applied throughout. Three Steps of Design 1. Ideation - A foggy idea of the design. You shoot a lot of arrows. A lot of them miss, but some of them hit. You calibrate to the one that hit and avoid the parameters used for the ones that missed. 2. Refinement - You generally hit the target but don't get the bullseye, and you are starting to understand your model. 3. Validation - When you run your validation studies, you know you are hitting the bullseye. Understanding and Predicting the ROI of High-Performance Computing

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