12 © 2016 ANSYS, Inc. August 28, 2018
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B11 A11 C11
A12 A2
B12 B2
C12 C2
ROT2 ROT1
ASMS
3~
M
J
STF
M(t)
GND
m
STF
F(t )
GND
Magnetics
JA
MMF
Mechanics
L
H
Q
Hydraulics, Thermal, ...
Simplorer Simulation Data Bus / Simulator Coupling Technology
Block Diagrams
State-Space
Models
Digital/
VHDL
JK-Flip flop
with Active-low
CLK
INV
CLK
CLK
J Q
QB
CLR
PST
Flip flop
K
CLK
CLK
INV
0
0 0 0 1
Curve
Data
ffjkcpal1.clk:TR
ffjkcpal1.j:TR
ffjkcpal1.k:TR
ffjkcpal1.clr:TR
ffjkcpal1.pst:TR
ffjkcpal1.q:TR
ffjkcpal1.qb:TR
MX1: 0.1000
PROCESS (CLK,PST,CLR)
BEGIN
IF (PST = '0') THEN
state <= '1';
ELSIF (CLR = '0') THEN
state <= '0';
ENDIF;
state
transition
AUS
SET: TSV1:=0
SET: TSV2:=1
SET: TSV3:=1
SET: TSV4:=0
(R_LAST.I <= I_UGR)
(R_LAST.I >= I_OGR)
EIN
SET: TSV1:=1
SET: TSV2:=0
SET: TSV3:=0
SET: TSV4:=1
State Graphs
Cx
y
Bu Ax x
=
+ =
Electrical Circuits
ANSYS Simplorer – Multidomain
