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Semantics of Synchronous Hypothesis (Theory)
• Existence of a discrete clock:
‐ Software cyclically activated
‐ Inputs are read at the beginning of the step (cycle) and are constant during the step
‐ No need to buffered streams, can run with a finite amount of memory during the step
‐ No cycle overlaps
‐ Outputs delivered at end of step
Reactions to stimuli are instantaneous
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